关键词:
Integrated circuit design
摘要:
To mitigate the increasing design complexity of very large scale integrated circuits (VLSI), the abstraction level design engineers work on has to be raised. In this paper, we propose an efficient UML-and SystemC-based design flow with performance, area and power coestimation at early stages and apply it to RSA and ECC crypto-Processor implementation. It is divided into several sections. Firstly, the UML class diagram is used to describe the target architecture and the UML sequence and state diagrams are used to describe the dynamic behavior of the design. Secondly, SystemC behavior models are translated from the UML models semi-automatically and TLM models are refined from SystemC behavior models. During SystemC behavior and TLM modeling process, the estimation methodology of performance, power and area is combined to facilitate architecture exploration. This can avoid extensive redesign, reduce cost/time and achieve good trade-off in power, area and performance. Thirdly, a hybrid simulation of TLM and RTL models is proposed to validate the refinement from TLM to RTL. The experimental results with performance, power, and area estimation at different abstraction levels are adopted to demonstrate the efficiency of the proposed design flow for RSA and ECC crypto-processor design. ©, 2015, Binary Information Press. All right reserved.